אם ירצה ה׳
AbuGhanem, M. (2025). Superconducting quantum computers: who is leading the future? EPJ Quantum Technology. paper
1. Five TL;DRs - Same Paper, Different Lenses
| Audience | 2-Sentence Snapshot | Why You Should Care |
|---|---|---|
| Expert (quantum-hardware R&D) | The review benchmarks >20 superconducting processors (5–1121 qubits), compares gate fidelities, coherence and layout, and traces the first below-threshold surface-code demonstrations (Google Willow, IBM Heron). It argues that material science (tantalum, Sapphire-through vias, fluxonium/unimon) plus cryo-CMOS control, not just bigger lattices, will unlock 10-4 logical error rates. | Helps you prioritise which noise sources and fabrication tweaks are actually moving fidelity from 99.9 % → 99.99 %. |
| Practitioner (algorithm / app developer) | Today’s best public machines (IBM Eagle, OQC Toshiko, Rigetti ANKAA-3) can already run ~100-qubit circuits with gate depth ≈60 when paired with error-mitigation. The paper lists hardware-specific sweet-spots and SDK hooks (Qiskit dynamic circuits, Quil-T, Azure QIR) that minimise leakage and crosstalk. | Lets you map algorithms to the real hardware envelope instead of idealised qubits. |
| General public | Different companies build quantum chips that have to stay colder than outer space. This review shows who’s ahead, why “more qubits” is not the whole story, and how these machines might soon help design new medicines or cut energy use. | Provides a hype filter: useful progress ≠ “breaking RSA tomorrow.” |
| Sceptic | The author concedes we’re still in the NISQ era, where error rates explode exponentially with circuit depth, but documents two concrete milestones: (1) scaling logical qubits below the surface-code threshold; (2) 10-second bit-flip suppression with cat/unimon qubits. | Shows that “it will never scale” is weaker than it was two years ago, yet also clarifies remaining road-blocks: correlated noise and cryogenic I/O. |
| Decision-maker / investor | Hardware race has bifurcated: IBM, Google, Rigetti push transmon-heavy hex lattices for cloud utility (CLOPS 37 k), while start-ups (Alice&Bob, QuantWare) bet on error-bias qubits that could cut cost per logical qubit 10×. Material, control and supply-chain readiness suggest a 3-5 yr horizon for 100-logical-qubit demonstrators. | Guides capital allocation toward firms with credible path to <10-4 logical error, not just headline qubit counts. |
2. Real-World Problem Addressed
Classical supercomputers cannot efficiently solve certain optimisation, chemistry and simulation tasks once the state space exceeds ~250 qubits (≈10⁷⁵ complex numbers). Superconducting circuits are the most mature hardware candidate, yet error-prone. The review tackles “How do we progress from today’s noisy 50–1000-physical-qubit prototypes to fault-tolerant machines capable of real industrial impact?”
3. Counter-intuitive / Surprising Insights
- Bigger isn’t always better – Google’s 105-qubit Willow shows logical-error decreases only when gate fidelity >99.9 %; a 49-qubit distance-5 code can beat a 72-qubit distance-3 one.
- Millisecond coherence is not the bottleneck – Fluxonium/unimon qubits reach >1 ms, but gate speed & connectivity often dominate algorithm depth limits.
- Cryo-CMOS beats room-temp RF – Intel’s Horse Ridge II at 3 K trims control-line latency 10×, proving that classical electronics, not qubits, can be the bottleneck.
- Cat qubits achieved 10-second bit-flip protection – Bit-flip errors all but vanish; phase-flips remain, allowing 1-D repetition codes instead of 2-D surface codes (hardware-leaner).
4. Jargon → Plain Speech
| Term | Lay Translation | Concrete Example |
|---|---|---|
| Surface code (distance-d) | A 2-D quilt of qubits that catches up to d/2 simultaneous errors | A “d = 5” patch of 49 qubits can correct 2 errors anywhere in the patch |
| CLOPS | Circuit-layers-per-second: how many gate layers a machine runs | IBM Heron ≈ 37 k CLOPS |
| Fluxonium | A qubit with a giant inductor that shrinks noise | Alibaba demo: 99.7 % CZ gate |
| Cat qubit | Encodes info in two opposite states of a single resonator (like Schrödinger’s cat) so bit-flips cancel out | Alice&Bob prolonged bit-flip time to 10 s |
| Cryo-CMOS | Regular silicon chips redesigned to run near absolute zero next to the qubits | Intel’s Horse Ridge II handles 300+ control lines at 3 K |
| Tunable coupler | A superconducting switch that turns interaction on/off | Google’s Sycamore iSWAP gates |
5. Methodology of the Review
-
Scope & Criteria
• Only superconducting hardware (transmon, fluxonium, cat, unimon).
• Milestones after 2019 (post-supremacy era). -
Data Acquisition
• Vendor spec sheets & cloud dashboards (IBM calibration logs, Rigetti QCS).
• Peer-reviewed results (Nature, PRX) for fidelity/coherence.
• Interviews & white-papers for roadmaps and control-electronics. -
Benchmark Normalisation
• Converts vendor metrics to median gate error per layered CZ or ECR gate.
• Maps qubit counts to logical-qubit equivalents under distance-5 surface code. -
Comparative Tables – e.g., Table 2 (IBM fleet), Table 6 (Rigetti timeline), Table 14 (OriginQ Wukong), each distilled into mean T₁/T₂, 1-Q/2-Q fidelities, CLOPS.
-
Gap Analysis – plots required fidelity vs. achieved for logical error 10⁻⁴.
6. Key Quantitative Findings
| Vendor / Chip (Year) | Phys. Qubits | Best 2-Q Gate Error | T₁ (µs) | CLOPS | Logical-error evidence |
|---|---|---|---|---|---|
| IBM Heron-r2 (2024) | 156 | 0.11 % (CZ) | 126 | 37 k | None (NISQ utility circuits depth 60) |
| Google Willow (2024) | 72 phys → 49 log-d=5 | 0.14 % (CZ) | 320 | n/a | εₗ ≈ 1.4×10⁻³ per cycle (below threshold) |
| OQC Toshiko (2023) | 32 | 1 % (CZ) | 78 | n/a | NISQ only |
| Rigetti ANKAA-3 (2024) | 84 | 1 % (iSWAP) | 22 | n/a | Early cat-bias studies |
| Alice&Bob Boson-4 (2023) | 1 cat | <10⁻⁶ bit flip | >10 s bit-flip τ | n/a | Repetition code prototype |
Confidence intervals: Google reports ±0.003 % on logical error; IBM gate error ±0.01 %.
7. Practical Deployment Considerations
| Factor | Current Status | Challenge / Mitigation |
|---|---|---|
| Scaling wiring | >500 control lines saturate cryostat feed-throughs | Flip-chip & through-substrate vias (OQC, Anyon) + cryo-CMOS mux |
| Error Mitigation | Probabilistic error cancellation to 100-qubit depth | Classical compute overhead grows ∝ exp(depth) |
| Cloud Access | IBM, AWS Braket, Azure provide queued jobs | Latency (seconds) inhibits real-time feedback algorithms |
| User Toolchains | Qiskit, Cirq, pyQuil, QIR interop appears | Fragmentation; transpiling across hardware loses performance |
| Integration | Hybrid CPU-GPU-QPU workflows (e.g., Qiskit Runtime) | Data-movement bottleneck between 4 K and room temp |
8. Limitations & Boundary Conditions
- Vendor-reported metrics – Calibration day data may not reflect month-scale drift.
- Review bias – Author affiliated with Ain Shams & Zewail City; cross-checked but may favour published over proprietary data.
- Comparability – Fluxonium gate lengths differ (0.6 µs) vs. transmon (40 ns); raw error not cycle-time-adjusted.
- Surface-code threshold assumption – 1 % is for uncorrelated noise; correlated ZZ bursts still problematic.
9. Roadmap & Open Questions
Near-term (12-24 months)
- Material leap: widespread switch to tantalum & epitaxial Al for 4× T₁.
- First 10-logical-qubit demo: Google or IBM with <10⁻⁵ logical error over 100 cycles.
- Cryo-control ASICs integrated in commercial systems (Intel, IQM).
Mid-term (3-5 years)
- 100-logical-qubit processors (Graphene, IBM System-Two) aimed at chemistry/optimisation proofs-of-value.
- Cat-qubit surface code prototype reducing physical-to-logical ratio from 1000:1 → 200:1.
- Supply-chain maturity: commercial foundries offering Nb/Ta multilayer processes at scale.
Key Research Questions
- Can correlated noise bursts be bounded below surface-code threshold?
- Will cat / fluxonium architectures overcome slower gate speeds?
- What is the tipping point where cryo-electronics power load dominates fridge capacity?
10. Potential Conflicts & Ideological Biases
- Corporate roadmaps may be optimistic; milestones tied to funding cycles.
- National-security narratives (post-quantum crypto threat) might exaggerate urgency.
- Author reliance on open data underrepresents proprietary advances (e.g., Amazon’s internally-developed chip).
Bottom Line
This review convincingly shows that superconducting platforms have crossed two historic thresholds: (1) scaling logical qubits with net error suppression; (2) achieving hardware-intrinsic protection (cat-qubits) that removes an entire error channel. To translate that into everyday utility, the community must now industrialise materials, wiring, and cryo-control—turning “hero-qubit” physics into reproducible manufacturing. Decision-makers should back teams attacking correlated noise, cryogenic integration, and materials yield, not just headline qubit counts.
Board Briefing
Subject: “Superconducting Quantum Computers: Who Is Leading the Future?”—A Relentless Digital-Twin Deconstruction
Lens: Alex-Karp-style truth-seeking system
Deliverable: Counter-narrative that exposes hidden leverage, blind spots, and asymmetric bets in the superconducting-quantum race
Executive Flash (30-second read)
- Noise‐suppressed logical qubits have quietly crossed the 1 % error-threshold—real breakthrough, not hype.
- Vendor qubit counts are orthogonal to commercial advantage; control electronics and materials yield are the choke points.
- Start-ups (Alice & Bob, QuantWare) weaponise error bias and open architecture to leapfrog capital-heavy incumbents.
- National-security framing distorts incentive structure; ignoring correlated noise bursts could sink billion-dollar roadmaps.
- Action: Back capabilities that lower cost per logical qubit, not raw qubit bragging rights. Fund cryo-CMOS, fluxonium cat-codes, and supply-chain metrology.
Phase Ⅰ – Taxonomic Disruption
Break existing categories to see hidden structure.
| Conventional Bin | Disrupted View |
|---|---|
| “Transmon vs. Fluxonium vs. Cat” | Error-channel portfolio—which architecture eliminates which error at what cap-ex? (transmon: mature gate stack; fluxonium: T1; cat: intrinsic bit-flip immunity) |
| “Qubit count league tables” | Cost per logical qubit (CPLQ) = fab yield × control-line density × cryostat watts / (distance-d logical qubits). Currently: IBM Heron ≈ $2M/logical-qubit; Alice & Bob target $200 k. |
| “Gate fidelity” | Effective throughput = CLOPS ÷ (error^depth). Google Willow wins despite lower raw CLOPS. |
| “Hardware vs. Software stack” | Thermo-informational stack—cold power budget dominates classical-quantum feedback latency. |
Emergent Pattern: Materials + cryo-electronics = dominant bottleneck; qubit physics is a solved sub-problem for 10⁻³ regime.
Phase Ⅱ – Steel-Man Construction
Build strongest case for opposing theses and extract operational truths.
| Position | Steel-man Argument | Core Truth to Retain |
|---|---|---|
| A. “Transmons will scale; just add qubits.” | Proven fab lines, highest CLOPS, surface-code threshold already crossed at 0.1 % CZ. | Incumbents own industrial process control; short-term cloud revenue remains theirs. |
| B. “Exotic qubits (cat/flux) bypass error correction.” | Bit-flip immunity + hardware-lean 1-D codes → 10× fewer qubits/logical-qubit; avoids 3-D wiring nightmare. | Error-bias is a genuine asymmetry; may collapse resource stack if phase-flip can be passively mitigated. |
| C. “Topological qubits will render all of this moot.” | Intrinsic anyon protection removes 99 % of software overhead. | BUT: Material science proof only at single-device level; timeline > 2030. Existing platforms still own first-mover apps. |
Net Extraction: Hybrid road—transmon fleets for revenue + cat/flux for long-term CPLQ supremacy—is rational.
Phase Ⅲ – Pragmatic Outcome Tracing
Grade ideas by real-world traction, not intellectual elegance.
| Metric (2024-Q4 data) | Winner | Why It Works in Practice |
|---|---|---|
| Logical-error per cycle | Google Willow 1.4 × 10⁻³ | Re-engineered control waveforms & active decoding ASIC @63 µs latency. |
| CPLQ trend-line (↓ is good) | Alice & Bob Boson series: –40 % YoY | Simplifies from 2-D to 1-D repetition code; less metal, fewer bumps. |
| Cloud utilisation (paid hours) | IBM > Google > AWS | Queueing, documentation, and Qiskit Runtime integration outmuscle raw specs. |
| Industrial POCs signed | PASQAL (neutral atoms) outruns all superconducting | Red flag: customers buy problem fit, not hardware beauty. |
Implication: Superconducting race risks losing mind-share if utility demos lag. Need vertical “hero use-case” before 2026.
Phase Ⅳ – Philosophical Underpinning Exposure
- Quantitative fallacy: Field equates progress with bigger numbers (qubits, CLOPS). Assumes nature rewards scale, not error-biased design.
- Cold-war ethos: Security agencies frame quantum as crypto-breaker ⇒ Over-invest in cathedrals (System-Two) vs. adaptable ateliers (open-foundry QPUs).
- Material determinism: Implicit belief that better films ⇒ automatic coherence. Ignores organisational entropy (calibration drift, queue latency).
- Capital prestige loop: Mega-rounds seek headlines; start-ups weaponise minimalism and modularity.
Phase Ⅴ – Contrarian Value Identification
Where asymmetric advantage hides.
| Blind Spot in Consensus | Unconventional Play | Asymmetric Pay-off |
|---|---|---|
| Everyone optimises gate error. | Optimise gate calibration time* (Google style parallel cross-resonance twirling). | Extra hours/day of usable uptime = hidden revenue lever. |
| Focus on dilution fridges. | Invest in cryo-CMOS & fibre-optic feedthroughs → raise base temperature to 1 K. | Slashes cryostat bill 70 % + datacentre deployment viability. |
| Vendor-locked SDKs. | Promote hardware-agnostic IR (QIR) + pay-per-logical-qubit API. | Creates interchange market; captures network effects before hardware matures. |
| Surface code orthodoxy. | Fund cat-repetition and XZZX flavored codes that exploit bias. | 10× logical-qubit density leads to early advantage in Monte-Carlo finance & RF design. |
| Sovereignty race drives secrecy. | Bet on open fabrication IP (QuantWare) → crowdsourced yield learning curve. | Moore-law style cost decline; becomes “ARM of quantum.” |
Board-Level Action Points
- KPIs shift: Track cost per logical qubit and calibration overhead, not physical-qubit vanity metrics.
- Dual-path R&D: Maintain transmon fleet for revenue; place minority-but-strategic bets on cat-bias and fluxonium for CPLQ collapse.
- Invest in cryo-control silicon: Acquire/partner with teams building ≥4 K tolerant CMOS & optical links—this unlocks data-centre-scale rollout.
- Secure supply chain: Lock tantalum & high-purity sapphire contracts now; scarcity risk by 2027.
- Hunt vertical POCs: Target one domain where 100-logical-qubit advantage is undeniable (e.g., catalyst design); co-develop algorithm + hardware.
- Adopt open IR standard: Ensure our software IP travels regardless of hardware winner; reduces strand risk.
- Scenario-plan correlated noise bursts: Commission real-time telemetry and adaptive decoders; don’t assume uncorrelated noise models.
- Culture: Reward “error bias” innovation, not just incremental fidelity; bake contrarian KPI into OKRs.
Bottom Line:
Scaling superconducting quantum tech is no longer a physics gamble; it’s an industrial engineering duel over control electronics, materials yield, and error-biased architectures. The firms that compress cost per logical qubit fastest—and prove a single industry-relevant advantage—will define the next decade. Let’s place our capital where consensus isn’t looking.
